Field of the Invention
This invention relates to the thermal modeling of semiconductor junctions, and more particularly to modeling the temperature profiles of transistor junctions on an integrated circuit (IC).
Description of the Related Art
The quest for an accurate understanding of the thermal properties of integrated semiconductor devices is driven both by a need for more efficient modeling of these devices for circuit level simulation, and also for reliability concerns. For example, a complete theoretical determination of the junction temperature near a high power transistor requires the coupled simulation of both the semiconductor device's electric equations and the heat equation. This combined electro-thermal problem is a significant challenge. A major feature of the heat problem is the need to simulate a very large region of the device and substrate; the length scale of a substrate is on the order of several millimeters, while the geometrical features of the transistor are in the micron or sub-micron range.
ICs containing high power electronics often consist of multiple rectangular-shaped field transistors (also referred to as “finger-shaped” transistors), such as the high-electron-mobility transistors (HEMTs) or heterojunction bipolar transistors (HBTs). For example, gallium nitride (GaN) integrated transistor devices often have a heat source area as small as ˜0.5×150 μm2, with a large aspect ratio (length-over-width) for each gate finger, and a substrate base as large as ˜2×2 mm2. One state-of-the-art method of determining thermal performance employs finite element analysis (FEA) or finite volume analysis (FVA) models. However, the wide difference in geometric scale noted above requires a very fine mesh near the heat sources to achieve accurate results from these mesh-based discretization computation models. A large number of meshed elements are required to ensure convergence of the solution, particularly when the relevant length scales of the heat sources vary significantly in the domain of interest. In particular, when the number of heat sources increase in a practical IC design, the mesh-size can grow to millions of degrees of freedom (DOFs), making rendering an efficient computation solution impractical.
On the other hand, an analytical solution of a Fourier series expansion requires a large number of terms to converge. As illustrated in FIGS. 1a-1d, the widely used analytical model solves for the temperature at the surface of a source plane consisting of multiple rectangular-shape transistor heat sources (such as transistor heat source 10 in FIG. 1a, also referred to herein as ‘finger-shaped’ or ‘a finger’) located on a rectangular prism domain of a substrate 12, with heat source 10 having a length ly and a width lx. The Fourier series expansion solution (FIG. 1b) consists of three infinite series summations, with two single summation terms and one double-summation term. Five such fingers are illustrated in FIG. 1c, with temperatures calculated across the substrate shown in FIG. 1d. It was reported in the literature that more than 1010 summation terms (m=105, n=105 terms, in the double series summation) are required to achieve a solution accuracy of 0.1% (see, e.g., Y. S. Muzychka, K. R. Bagnall, and E. N. Wang. “Thermal spreading resistance and heat source temperature in compound orthotropic systems with interfacial resistance,” IEEE Trans. Components, Packaging, and Manufacturing Technology, vol. 3, no. 11, Nov. 2013, pp. 1826-1841). As a result, the analytical solution of a Fourier series expansion with a double-summation term is not practical for efficient thermal simulation of ICs with finger-shaped transistors having high aspect ratios.
Integrated circuit designers often choose to adopt conservative layouts when designing such high power circuits, due to uncertainty with respect to the thermal coupling effect between transistors, overall device performance, and reliability. As a result, a circuit layout that provides optimal circuit performance may be impractically large.